A Queueing Model of a Bufferless Synchronous Clos ATM Switch with Head-of-Line Priority and Push-Out

We consider a synchronized bufferless Clos ATM switch with input cell processor queues. The arrival process to each input port of the switch is assumed to be bursty and it is modeled by an Interrupted Bernoulli Process. Two classes of cells are considered. Service in an input cell processor queue is head-of-line without preemption. In addition, push-out is used. That is, a high priority cell arriving to a full queue takes the space occupied by the low priority cell that arrived last, as long as the cell is not in service. Each cell processor queue is modeled as a priority IBP /Geo/l/K+l queue with pushout. We first present an exact analysis of this priority queue.The results obtained are then used in an approximation algorithm for the analysis of the ATM switch. Validation tests using simulation data shows that the approximation algorithm has a good accuracy. •Supported in part by DARPA under grant no. DAEA18-90-c-0039.